1. Field of the Invention
Embodiments of the invention generally relate to electronics, and in particular, to data communication links.
2. Description of the Related Art
FIG. 1 illustrates an example of a serial communication link with clock and data recovery (CDR). A physical layer of a computer network includes the underlining physical devices of the computer network. For example, with reference to FIG. 1, at the physical layer, a serial data communication link can include: a transmitter (Tx) 102, a communication channel 104, and a receiver (Rx) 106.
The transmitter (Tx) 102 converts a clocked digital data stream to an analog stream (thereby embedding a clock signal in the serial data stream). The communication channel 104 can introduce linear distortion, non-linear distortion, and noise. The receiver (Rx) 106 recovers the embedded clock signal and data from the distorted serial data stream.
A serial data communication link can also use an analog-to-digital converter (ADC) and digital signal processor (DSP)-based clock and data recovery (CDR) receiver 202 as illustrated in FIG. 2. In the CDR receiver 202, the distorted serial data stream is converted from analog to digital via the ADC, and then the digital version of the distorted serial data stream is processed in digital domain to extract the data and the embedded clock signal.
FIG. 3A illustrates further details of one example of the CDR receiver 202. The illustrated CDR receiver 202 includes a programmable gain amplifier (PGA) 302, an analog-to-digital converter (ADC) 304 a feedforward equalizer (FFE) 306, a first summing circuit 308, a decision feedback equalizer (DFE) 310, an equalizer 312, a phase detector (PD) 314, a second summing circuit 316, an amplifier 318, a filter 320, a clock pulse (CP) generator 322, a slicer 324, and a least means squares (LMS) adaptation processor 326. Some of the components illustrated in FIG. 3A can be optional.
The CDR receiver 202 operates as follows. The PGA 302 receives and amplifies the distorted serial data stream. The gain of the PGA 302 can be adjusted. The ADC 304 converts the distorted serial data stream from analog to digital. While the output of the ADC 304 may be digital, the data stream is still in soft symbol form and has not yet been sliced to hard symbols. The digital version of the distorted serial data stream is then provided as an input to the FFE 306 and to the equalizer 312. For example, the FFE 306 can provide equalization, such as pre-emphasis, that is complementary to the characteristics of the communication channel 104 (FIG. 2), which typically has a low-pass characteristic. The DFE 310 and the first summing circuit 308 can provide additional equalization that is dependent on one or more prior symbols to reduce inter symbol interference (ISI). The LMS adaptation processor 326 can adjust filter coefficients of the FFE 306 and/or the DFE 310. The output of the DFE 310 can then be sliced to convert symbols from soft symbols to hard symbols for decoding of data symbols.
The equalizer 312 can also provide equalization for the timing recovery path and provide an equalized signal as an input to the PD 314. The equalizer 312 is typically smaller and lower power than the equalizers 306, 310 of the data recovery path. The PD 314 determines a phase difference between the equalized signal and an output of the slicer 324. The output of the PD 314 is summed with a PD offset, then amplified by a PD gain, then low-pass or band-pass filtered by the filter 320, which then controls the CP generator 322. The CP generator 322 can be implemented in a variety of ways. For example, the CP generator 322 can be a numerically controlled oscillator (NCO) controlled by the output of the filter 320. In another example, the CP generator 322 can be a phase interpolator that receives a fixed clock frequency input and generates a different phase of that input fixed clock. The output of the CP generator 322 corresponds to the recovered clock signal.
FIG. 3B illustrates a Mueller-Muller phase detector. See, MUELLER, K. and MULLER, M., Timing Recovery in Digital Synchronous Data Receivers, IEEE Transactions on Communications, May 1976. That paper describes a timing recovery loop that is used in many baud-rate sampling serial links.
For timing recovery, a Mueller-Muller phase detector 350 first estimates the impulse response of the channel 104 (FIG. 1). It should be noted that the impulse response of the channel 104 is typically not directly available. Rather, the digitized data stream is typically all that is observable. Mueller-Muller then outline various ways to use a sampled impulse response h(t) 370 for phase detection; the most common way is to achieve phase lock by forcing the pre-cursor sample 372 and the post-cursor sample 374 of the sampled impulse response h(t) 370 to be at the same level. If the sampled impulse response h(t) 370 is symmetric about the cursor, this should force the main cursor sample 376 to be located right on the peak, which is considered to be desirable in the prior art.